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<Paper uid="H90-1097">
  <Title>Real-Time Speech Recognition Systems</Title>
  <Section position="1" start_page="0" end_page="425" type="abstr">
    <SectionTitle>
SRI International
</SectionTitle>
    <Paragraph position="0"> Objective: SRI and U.C. Berkeley have begun a cooperative effort to develop a new architecture for real-time implementation of spoken language systems (SLS). Our goal is to develop fast speech recognition algorithms, and supporting hardware capable of recognizing continuous speech from a bigram or trigram based 20,000 word vocabulary or a 1,000 to 5,000 word SLS systems.</Paragraph>
    <Section position="1" start_page="0" end_page="425" type="sub_section">
      <SectionTitle>
Recent Accomplishments
</SectionTitle>
      <Paragraph position="0"> * We have designed eight special purpose VLSI chips for the HMM board, six chips at U.C. Berkeley for HMM beam search and viterbi processing, and two chips at SRI for interfacing to the grammar board.</Paragraph>
      <Paragraph position="1"> * SRI and U.C. Berkeley have completed simulations of each of the special purpose VLSI chips.</Paragraph>
      <Paragraph position="2"> * U.C. Berkeley has completed the fabrication of one printed circuit board, for the HMM output probability computation.</Paragraph>
      <Paragraph position="3"> * By reimplementing SRI's Natural Language Parser from PROLOG to C, SRI was able to decrease the parse time by a factor of three.</Paragraph>
      <Paragraph position="4"> * SRI modified SRI's language processing algorithms to implement a continuum between SRI's Dynamic Grammar Network (DGN) and BBN's N-best algorithm, to balance the computational load between the HMM speech recognizer and the SLS parser.</Paragraph>
      <Paragraph position="5">  tion performance; on the standard training set this improves speaker-independent perplexity 60 performance from 6.7% error to 5.1% error, and for a larger training set (about 11,000 sentences), improves speaker-independent recognition from 5.3% error to 4.1% error.</Paragraph>
      <Paragraph position="6">  * Complete the construction of the current hardware design, and develop software tools to support, this architecture.</Paragraph>
      <Paragraph position="7"> * Develop a large vocabulary recognizer to fully use the capabilities of this design.</Paragraph>
      <Paragraph position="8"> * Design, implement, and evaluate algorithms for real-time grammar processing computation.</Paragraph>
      <Paragraph position="9"> * Evaluate the current architecture to determine the computational and algorithmic bottlenecks.</Paragraph>
      <Paragraph position="10"> * Replicate the system and port to a DARPA and NASA site.</Paragraph>
    </Section>
  </Section>
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